Although the present invention is described with reference to memory components, the invention is not restricted thereto.
Memory components are connected to one another via a bus system, for example. The wiring paths provided, in particular of the signal lines, should be as short as possible. One technique provides for stacking memory components. The length of the wirings between contacts which are located above one another is kept short in this manner. FIG. 11 illustrates one known arrangement of housed semiconductor components 5. Two housed semiconductor components are placed on top of one another and are electrically connected to one another via the external wiring 3. FIG. 12 illustrates another arrangement for stacking. In this case, two unhoused semiconductor components 2 are placed on top of one another within a housing and are electrically connected by means of respective internal wiring 1 to the external wiring 3 of the housing. FIG. 13 illustrates another variant. In this case, two semiconductor components 2 are grouped around an intermediate layer 6 in the apparatus 8 and the individual semiconductor components are once again connected via internal wiring 1 to the external wiring 3 of the housing. FIG. 14 illustrates a fourth variant which differs from the previous arrangement by virtue of the fact that two semiconductor components 12 are stacked within a housing, an internal wire connection 1 and an interposer substrate forming the connection to the external supply lines, in the form of solder balls 16 in this case.
The impedance of the wirings between the contact regions 10 of the individual semiconductor components which are connected to one another is disadvantageously not matched in all four of the known semiconductor apparatuses presented. In particular, there is no provision for matching the impedance of the bonding wires having a typical length of the order of magnitude of 1 mm. Future memory generations having signal components in the frequency range of >1 GHz cannot be applied using these bonding wires.
Another problem results for bus systems having branches in the signal lines. In this case, it is not easily possible to match the impedance of all wiring sections without additional capacitances and inductances. Bus systems therefore always have sections with poor impedance matching.
This results in the problem of the performance of future memory components being restricted by signal reflections and interference effects on account of the wiring.